The present application relates generally to an improved data processing apparatus and method and more specifically to mechanisms for avoiding cross-interrogates in a streaming data optimized L1 cache.
On-chip co-processors are becoming increasingly popular to solve standard problems with specialized hardware attached to general purpose processing cores. Often, these co-processors work on data that has streaming characteristics, such as encryption, decryption, compression, etc. Potentially, co-processors create very large amounts of data in sequentially increasing memory addresses and make this data available to processor cores on the same chip, on other chips in a multiple chip environment, and/or written back into memory.
Existing solutions either provide a special store path directly into one or multiple processor cores in the same chip and let the processor core take care of storing the data through its normal store mechanisms or add another level one (L1) cache level for the co-processor, referred to as the “COP cache,” into the storage hierarchy and take care of data transfer through existing, well-known cache/memory hierarchy means.
Providing a special store path adds considerable functional complexity, and due to limitations of available silicon area and wiring constraints, the special store path is typically a narrow and slow path that is not well-suited for streaming data.
Adding another L1 cache level means that the co-processor's L1 cache has to get write (exclusive) access to a cache line. In existing implementations, this implies that any other L1 cache that needs access to the data must send special invalidation requests (exclusive cross-interrogates (XIs)) to the co-processor's L1 cache. The cache line may only be used if these XIs are acknowledged by the COP-cache, or there is an implicit scheme that assumes an acknowledge after some specified time. Because this always involves waiting for each cache line that was in use in the COP-cache, these XIs have significant performance impact.